1. Field of the Invention
This invention relates to the fabrication of electronic devices and, more particularly, to the fabrication of planarized isolation regions for separating semiconductor regions in devices and integrated circuits.
Co-pending U.S. patent application Ser. No. 173,481 by P. Zdebel et al., entitled "Planarization of Semiconductor Devices Having Surface Protrusions of Varying Width and Separation" (hereafter Zdebel-I) is related.
2. Background Art
It is well known in the semiconductor art to provide dielectric regions in semiconductor substrates for electrical isolation. Dielectric isolation is used to reduce interaction and parasitic capacitance between adjacent semiconductor regions and to reduce parasitic capacitance between the semiconductor substrate and overlying conductors used for interconnection purposes.
Silicon is the most commonly used semiconductor and silicon oxide is the most commonly used isolation dielectric because of its excellent compatibility with silicon. However, other semiconductors and isolation dielectrics are also used. The terms "dielectric isolation" and "oxide isolation" are employed herein to refer generally to isolation regions which comprise an electrical insulator. The isolation region may be entirely of a dielectric or may be a combination of a dielectric and a conductor, as for example a dielectric liner or sidewall with a polycrystalline semiconductor core.
For convenience of explanation, the invention is described using silicon as an exemplary semiconductor material. However, this is not intended to be limiting and those of skill in the art will appreciate that other semiconductors (e.g., III-V's, II-VI's) can also be used. Those of skill in the art will also appreciate that many different dielectrics can be used, of which oxides, nitrides, oxy-nitrides, and layered structures are examples. Silicon oxide, silicon nitride and combinations thereof are preferred dielectrics.
When dielecric isolation is employed to create isolated semiconductor device islands, it is desirable that the isolation regions have as planar a surface topology as possible so that further processing needed to form the desired devices and interconnections may be readily carried out. An important requirement is that the isolation process induce as few defects as possible in the semiconductor islands so as to minimally affect the semiconductor properties (e.g., carrier lifetime, recombination velocity, mobility, etc.) and resulting device properties. A further requirement is that the isolation process be as simple as possible so as to promote high yield and low manufacturing cost.
A wide variety of oxide isolation processes are known, as for example, LOCOS (Local Oxidation Of Silicon) and ROI (Recessed Oxide Isolation). However, these and other prior art isolation processes suffer from a number of well known limitations which become increasingly severe as one attempts to construct devices and circuits of ever greater complexity, packing density, and performance. As critical device dimensions are reduced it is found, for example, that such prior art processes do not scale in proportion to the device scaling and, among other things, lead to an increased proportion of wasted chip area. Such processes often lead to undesirable "bird's beaks" in the wafer surface where the isolation region meets the semiconductor island. Further, such processes can also cause powerful residual stresses in the semiconductor island. These effects degrade performance and increase cost.
Accordingly, it is an object of the present invention to provide an improved means and method for forming dielectric isolation regions in semiconductor substrates wherein the isolation regions are planarized with respect to the semiconductor surface.
It is a further object of the present invention to provide such planarized dielectric isolation regions while minimizing defect formation in the semiconductor islands being isolated.
It is another object of the present invention to provide such planarized dielectric isolation regions and minimum defect formation in the semiconductor islands being isolated while maintaining precise dimensional control of the isolation regions and semiconductor islands.
It is a further object of the present invention to provide such planarized dielectric isolation regions while minimizing defect formation in the semiconductor islands being isolated using a process which is both simple and highly compatible with other process steps to improve manufacturability and reduce cost.
It is another object of the present invention to provide such planarized dielectric isolation regions and minimum defect formation in the semiconductor islands being isolated using a process employing comparatively short times at elevated temperatures, i.e., small Dxt (Diffusivity x time) product so as to minimize adverse impact on previously doped device regions.
As used herein, the words "planarized" or "planarization" are intended to refer to structures which have a substantially smooth upper surface, substantially free of abrupt steps, protrusions or depressions, and where the height of any residual abrupt surface features or steps is small compared to the thickness of subsequent layers intended to bridge or fill such features or steps. While it is desirable that the planarized surface also be substantially flat, smoothness is more important than flatness and absolute flatness is not required.